ES 210: Digital Circuits and Logic Design

(Prerequisite: ES 230 and 231, or equivalent)
Spring 2008 Semester

Instructor	Office	Tel	Fax	Email	Office Hour
Jagan Agrawal	Salazar 2004	(707) 664-4438	(707) 664-2361	jagan.agrawal@sonoma.edu	M-F 10-11 am, or by appointment
Ali Kujoory	Salazar 2005	(707) 664-2030	(707) 664-2361	ali.kujoory@ieee.org	M 4:30-5 pm, Tu/Th 11:45 am-12:30 pm, or by appointment

CLASS TIMINGS:

Lectures: Tuesdays and Thursdays, 10:30 a.m. to 11:45 p.m. in Salazar #2009A.
Laboratory: Fridays, 2 p.m. to 4:50 p.m. in Salazar #2003 (by Mr. Shahram Marivani).
Lectures for this course start on Jan. 29 and end on May 15.
No classes during the week of March 24 due to the Spring Break.

COURSE OBJECTIVES:

The objectives of this course are to:

introduce the concept of digital and binary systems
give students the concept of digital electronics
provide fundamental concepts used in the design of digital systems
give students the basic tools for the design and implementation of digital circuits, modules and subsystems
reinforce theory and techniques taught in the classroom through experiments and projects in the laboratory.

COURSE SYLLABUS AND WEEKLY INSTRUCTION PLAN:

Week 1: (Jan 29, Jan. 31)
REVIEW OF BINARY SYSTEMS, BOOLEAN ALGEBRA AND LIGIC GATES.
Digital Systems. Binary Numbers. Number Base Conversions. Octal and Hexadecimal Numbers. Complements. Signed Binary Numbers. Binary Codes. Binary Storage and Registers. Binary Logic. (Chapter 1)

Axiomatic Definition of Boolean Algebra. Basic Theorems and Properties of Boolean Algebra. Boolean Functions. Canonical and Standard Forms. Other Logic Operations. Digital Logic Gates. Integrated Circuits. (Chapter 2)

Week 2: (Feb. 5 & 7)
REVIEW OF OPTIMIZATION OF BOOLEAN FUNCTIONS AND GATE LEVEL IMPLEMENTATIONS, AND, INTRODUCTION OF A LANGUAGE FOR DESCRIBING AND TESTING IMPLEMENTATIONS (HARDWARE).
The Map Method of Boolean Function Representation. Four-Variable Map. Five-Variable Map. Product of Sums Simplification. Don't-Care Conditions. NAND and NOR Implementation. Other Two-Level Implementations. Exclusive-OR Function. Introduction and Application of Hardware Description Language (HDL). (Chapter 3) (HDL Examples)

Week 3: (Feb. 12 & 14)
DESIGN AND IMPLEMENTATION OF DIGITAL BUILDING BLOCKS - I
Combinational Circuits, Analysis Procedure, Design Procedure, Binary Adder-Subtractor. Decimal Adder. Binary Multiplier. (Chapter 4)

Week 4: (Feb. 19 & 21)
DESIGN AND IMPLEMENTATION OF DIGITAL BUILDING BLOCKS - II
Magnitude Comparator. Decoders. Encoders. Multiplexers. HDL For Combinational Circuits. (Chapter 4) (HDL Examples)

Weeks 5 and 6: (Feb. 26, Feb. 28, March 4 and March 6)
DESIGN AND IMPLEMENATION OF SYNCHRONOUS SEQUENTIAL CIRCUITS.
Clock and Clocked Circuits. Sequential Circuits. Memory Elements. Latches. Flip-Flops. State of a Sequential Circuit. State Diagrams. Analysis of Clocked Sequential Circuits. HDL For Sequential Circuits. State Reduction and Assignment. Design Procedure. (Chapter 5) (Tables)

Test #1 on March 11

Weeks 7 and 8: (March 13, 18 and 20 and April 1)
DESIGN AND IMPLEMENTATION OF REGISTERS AND COUNTERS.
Registers. Shift Registers. Ripple Counters. Synchronous Counters. Other Counters. Random Sequence Generators. HDL for Registers and Counters. (Chapter 6)

Weeks 9, 10: (April 3, 8, 10, 15, and 22)
MEMORY AND PROGRAMMABLE LOGIC.
Introduction. Random-Access Memory. Memory Decoding. Error Detection and Correction. Read-Only Memory. Programmable Logic Array. Programmable Array Logic. Sequential Programmable Devices. (Chapter 7)

Week 11: (April 17, 29 and May 1) (Dr. Kujoory)
ASYNCHRONOUS SEQUENTIAL LOGIC.
Introduction. Analysis Procedure. Circuits With Latches. Design Procedure. Reduction of State and Flow Tables. Racing in Digital Circuits, Race-Free State Assignment. Hazards. Design Example. (Chapter 9 figures ) (Chapter 9 with text)

Test #2 on April 24

Weeks 12, 13 and 13.5: (May 6, 8, and 13) (Dr. Kujoory)
DIGITAL ELECTRONICS, TECHNOLOGY AND INTEGRATED CIRCUITS.
Introduction. Special Characteristics. Bipolar-Transistor Characteristics. RTL and DTL Circuits. Transistor-Transistor Logic (TTL). Emitter-Coupled Logic (ECL). Metal-Oxide Semiconductor (MOS). Complementary MOS (CMOS). CMOS Transmission Gate Circuits. Switch-Lever Modeling With HDL. (Chapter 10 figures) (Chapter 10 with text)

Week 14: (May 15)
REVIEW OF THE COURSE AND DISCUSSION ON FINAL EXAM.

Text Book:

‘Digital Design’, 4th edition, by M. Morris Mano and Michael D. Ciletti, published by Prentice Hall, 2007, ISBN: 0-13-198924-3.

Homework Assignments

References:
Please see the attached list.

Outcomes:
In this course, the students will attain:

an ability to apply knowledge of mathematics, science, and engineering.
an ability to design and conduct experiments, as well as to analyze and interpret data.
an ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability.

Grading Policy
Homework assignments	15%
Test #1 (Tuesday, March 11)	20%
Test #2 (Thursday, April 24)	20%
Final Exam (Tuesday, May 20, 11 a.m. to 12:50 p.m.)	20%
Laboratory	25%

Grades will be curved.

Policy on the Submission of Homework and Project Work:

All homework, experiments and projects must be done individually unless instructed otherwise.
All work must be submitted on 8.5 X11 papers.
Tables and graphs in the homework submissions must be presented neatly, properly labeled and must be clearly explained.
Each submission is due in the beginning of the class on the specified date.

Failing any of the above, a submission may not be accepted resulting in the loss of grade in that assignment.

Deadlines to drop the course:

Last day to drop with a differential in fee status: Friday, Feb. 8.
Period to drop with a ‘W’: Feb. 9 to 22.

List of References

Digital Design: Principles and Practices:4/e
© 2006 | Prentice Hall | Cloth; 928 | Instock
ISBN-10: 0131863894 (in new system: ISBN-13: 9780131863897)
John Wakerly

Digital Electronics: A Practical Approach:7/e
© 2005 | Prentice Hall | Cloth; 928 | Instock
ISBN-10: 0131141651 | ISBN-13: 9780131141650
William Kleitz

Digital Principles and Design with CD-ROM, 1st Edition
Donald D. Givone, SUNY BUFFALO
Hardcover with CDROM
©2003, ISBN-13 9780072551327

Introduction to Logic Design with CD ROM, 2nd Edition
Alan B Marcovitz, FLORIDA ATLANTIC U-BOCA RATON
Hardcover with CDROM, 672 pages
©2005, ISBN-13 9780072951769

Fundamentals of Digital Logic with VHDL Design with CD-ROM, 2nd Edition
Stephen Brown, University of Toronto, Canada
Zvonko Vranesic, University of Toronto, Canada
Hardcover with CDROM
©2005, ISBN-13 9780072499384

CMOS Digital Integrated Circuits Analysis & Design, 3rd Edition
Sung-Mo (Steve) Kang, UNIV OF CALIF-SANTA CRUZ
Yusuf Leblebici, Swiss Federal Institute of Technology
Hardcover, 672 pages
©2003, ISBN-13 9780072460537

Digital Design
Frank Vahid, Univ. of California, Riverside
Hardcover, 552 pages
©2006, ISBN: 978-0-470-04437-7

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