CES 520 - WEEK 10 October 24, 2006 - Designing With Customizable Logic Devices

CES 520 - WEEK 10 October 24, 2006 - Designing With Customizable Logic Devices

Types of Customizable Logic Devices

ROM memory can be used as a programmable logic device

Very flexible: allows any output for any input
No registers - usually must add external flip-flops
Slower than sequential logic
Inefficient use of silicon

Expensive
Relatively high power

SPLD - Simple Programmable Logic Devices

A few hundred gates
PAL - Programmagle Array Logic

Invented by MMI in 1978
"Sum of products"

OUTPUT = (A * B * C * ...) + (D * E * F * ...) + ... = (A & B & C) OR (C & D & E)

16V8 array
Output macrocells include output registers and additional signal routing
One-time programmable
Useful for "glue logic" replacement
For volume production, "HAL" (hard-array logic) mask-programmed devices are available

PLA - Programmable Logic Array

A PAL with the OR array programmable as well as the AND array.

GAL - Generic Array Logic

Invented by Lattice Semiconductor in 1985
Reprogrammable version of PAL
Output macrocells are also programmable.

Allows reconfiguring each pin as input or output, registered or combinational.

CPLD - Complex Programmable Logic Devices

Thousands to 10's of thousands of gates
Typically programmed in-circuit using JTAG or proprietary serial port

Generally non-volatile programming

Architecture based on PAL sum-of-products arrays.

Allow many more AND terms per OR gate.

Many parts are like an array of PALs with programable interconnects.
Each PAL-like section is called a macrocell
Like SPLDs, most macrocell I/O goes to device pins.

Minimal capability for internal state storage or deeply-layered logic.

FPGA - Field Programmable Gate Array

Tens of thousands to millions of gates
Compared to an ASIC, has low NRE (non-recurring engineering) cost, high per-part cost.

Good for prototyping or low-volume applications.

Organized into CLBs (complex logic blocks)

Each CLB is similar to a small PLA, with configurable logic and output registers.
Typically use LUTs (RAM look-up tables) to implement the combinational logic.
IOBs (I/O blocks) also contain registers and can be configured as input, output, or bidirectional.
The interconnections between blocks is much more flexible and complicated than in CPLDs.

Typically programmed in-circuit like a CPLD

However most FPGAs use volatile memory
Typically programmed from a PROM or on-board processor at power-up

Some parts have embedded memory, multipliers, microprocessore, etc

e.g. Xilinx Virtex-2 Pro: up to 2 Power PC cores, 444 hardware multipliers, 1 Mbyte RAM.
Embedded cores can be optimized much better than building the function with CLBs.

Vendor typically sells IP cores.

e.g. Xilinx's embedded "Microblaze" microprocessor

ASIC - Application-Specific Integrated Circuits

Up to over 100 million gates
Generally faster, lower power, and smaller chip size than equivalent-technology FPGAs.
NRE charges typically hundreds of thousands of dollars. Low per-part cost.

Good choice for high-volume applications.

IP cores may be purchased from third parties.

May be generic HDL or a fully-routed design specific to a specific IC manufacturer's process.

Gate array designs

A "sea of gates" is connected by programmable interconnections to generate the desired circuitry.

Typically no more than 50-75% utilization of chip resources is possible.

"Semi-custom" technique, uses a gate array like in an FPGA, but with hard-wired interconnections.
Typically only the last few layers of metallization are custom.

Lower NRE than standard cell but typically lower performance.

Resource utilization better than FPGA but still not 100%.
Often includes large IP cores, such as microprocessors, DSP, memory, I/O, etc.

Standard Cell designs

Each cell is a higher-level function.
Manufacturers have large libraries of standard cells for different functions.
Cells may be placed anywhere on the chip to optimize propagation delay.

Much of the chip area is needed for interconnects.

Improves speed because of the optimized design of each cell.
Allows synthesis vendors to develop standard libraries with known performance.

Full custom designs.

Advantages:

Potentially better performance
Lower per-unit cost
Ability to include analog/RF circuitry

Disadvantages:

Higher NRE cost
Longer design time
Higher design risk compared to using standard, pre-tested libraries

CPLD/SPLD design process

A single software tool generates the JEDEC file

JEDEC = Joint Electron Devices Engineering Council. Standard file format for PLDs.
PALASM "PAL Assembler"

For simple industry-standard PAL/GAL devices
Developed by MMI, given away free
Enter logic equations in an ASCII (.pds) file
Outputs JEDEC (.jed) files for programming devices
Can also include test vectors in the file.

The programming device tests the part after programming.

Data I/O made popular programming devices (models 60A and 2900)

ABEL is another PAL design tool

Created by Data I/O in 1983. ABEL is now owned by Xilinx.

CUPL:

For CPLDs as well as SPLDs
Design is specified at a higher level than Palasm. Software generates the logic equations.
Includes a simulator using test vectors generated by the user.
CUPL was invented by Logical Devices, Inc. Now supported by Altium.
"WinCUPL" is available free for download from Atmel's web site.

Some tools allow schematic entry.

A programming device burns the part from the JEDEC file

Data I/O is one of the most prominent suppliers.

ASIC/FPGA design process

(NOTE: Costs listed are for the base product. Add-ons add considerably to the final price.)
Complex process, involving a large number of often-incompatible tools. Beyond the scope of this course.
The major steps are numbered below. Similar process for ASICs and FPGAs.
1. Generate the design requirements at a high level

The farther along the design process, the more expensive changes become, especially for ASICs.

2. Simulate the design at a high abstraction level using some tool(s)

Tools to simulate mathematical algorithms

Matlab (Mathworks)

Matrix/vector paradigm ("Matlab" = "MATrix LABoratory")
Programming language-type interface.
Programs are called "M-files".
Can implement user interfaces.
Has fancy plotting capability
Can do symbolic math with the Maple engine
Very popular in academia
Cost $1900, $99 student version

Mathcad (Mathsoft)

Spreadsheet-like paradigm
Word-processor-like interface.

Equations look like textbook equations. (Greek letters, integrals, etc.)
Source code can serve as the final documentation.
Easier learning curve than Matlab

Easy-to-use plotting capability
Can do symbolic math with the Maple engine
Cost $895, $130 student version

Maple (Waterloo Maple Inc, a.k.a. Maplesoft)

User interface similar to Mathcad
Cost $900, $120 student version

Mathematica (Wolfram Research)

Default user front-end uses a notebook metaphor

Extensive layout and graphical capabilities
Free MathReader software allows viewing (but not editing) without a license

webMathematica software allows interface to a web site
Cost $1880, $140 student version

Tools to simulate the functional design, concentrating on numerical computations

This is functional verification, to assure the design conforms to specification.

Bit-level simulation is important to include truncation/rounding effects of finite word length.

Simulink* (Mathworks, built upon Matlab)

Ideal for simulating systems that can be described mathematically, such as DSP.
Cost: $2800, (student version included with Matlab).

SPW* Signal Processing Worksystem\\\\\\\\\\ Designer (Coware, ex-Cadence)

Oriented toward simulating digital signal processing algorithms and systems.
Block diagram editor supports both floating-point and bit-accurate representations.
"SigCalc" function is a powerful tool for generating and analyzing multi-bit signals.

ADS (Agilent)

Oriented toward RF/microwave systems
Cost $8400

System Studio* (Synopsis)

Complete system-level modeling and synthesis.
Supports SystemC modeling language.
"DesignWare" is their suite of IP modules

MATRIXx (National Instruments)

Mathematical analysis, simulation, documentation, and C code generation.
Cost $1695

Ascet-SD (ETAS)

Oriented toward automotive applications

Many designers simulate in C or another high-level programming language.

SystemC* is an extension to C++ to describe and simulate digital systems.

3. Generate HDL (Hardware Description Language)

May be generated automatically by the simulation tool (those marked with * above)
and/or hand-written code
Control-related functions are often hand-written directly in HDL, although tools are available:

StateFlow (Mathworks, built upon Matlab)

Cost: $2800, $59 student version

Tau (Telelogic)
Esterel Studio (Esterel Technologies)

Hardware description languages

Unlike traditional sequential programming languages, can easily describe parallel processes.

HDL languages can express the time that events occur.
Parallelism more closely represents real hardware.

The two main HDLs are VHDL and Verilog
VHDL

Originally developed by the Dept. of Defense
IEEE Std 1076
Syntax is subset of Ada programming language.
Strongly-typed: Many data types available
Language extensions add mixed-signal support. (VHDL-AMS)
Can write testbenches in VHDL to test the design

Many VHDL constructs are non-synthesizeable, used only for prototyping and simulation.

Verilog

IEEE Std 1364
Syntax similar to C
Includes mixed-signal support. (Verilog-AMS)
Like VHDL, can write test benches using synthesizeable and non-synthesizeable constructs.

SystemC

A set of libraries that extend the C++ programming language to model digital systems
Considerable syntactical overhead compared to VHDL/Verilog
Allows description and simulation using the same tool.

IC vendors as well as third parties sell pre-tested IP cores.

Reduces design time and risk.

If necessary, merge HDL from different sources
(Especially for ASICs) By some means verify that the design meets requirements

Write test bench (in HDL). Partially simulates the environment the ASIC/FPGA goes into.
Use an HDL simulation tool to verify correct operation, e.g.

ModelSim (Mentor Graphics)
NC-Sim (Cadence)
Incisive (Cadence)
VCS / Scirocco (Synopsis)

Generate test vectors (sequences of input or output values)

4. Logic systhesis: generate gate-level (or standard-cell-level) netlist from the HDL using some tool

Design Compiler (Synopsis)
RTL Compiler (Cadence)
Leonardo Spectrum (Mentor Graphics)
Synplify (Synplicity)

Verify the equivalence of the resulting netlist to the HDL

A gate-level simulator may run too slowly for large designs.

Test vectors must be short - less than full coverage.

Or use a formal verification tool - uses algorithms based on the same laws as the synthesis tool.

Essentially another netlist synthesizer, but written by different designers so with different bugs.

Do initial (static) timing analysis using some tool, e.g.

PrimeTime (Synopsis)
CeltIc (Cadence)
TimeQuest (Altera)

5. Place and route: A software tool to lay out the chip
Software typically provided by the chip vendor.
If the P&R tool can't meet timing requirements, go back and iterate the design
"Extraction": A verification tool that extracts models from layout masks and compares to netlist
(Mostly for ASICs) Simulate using previously-generated test vectors.

Should get same response as from the HDL.
At this level, simulations are VERY slow. Again, formal verification is an option.

6. Make the part

FPGA:

Program FPGA directly, program its boot rom, or generate FPGA image for download by mP
FPGAs often used in ASIC design for verification purposes

May take several large FPGAs to simulate one ASIC
Probably won't run at full speed

ASIC:

Send in design to vendor for fabrication
Pay the million-dollar NRE charge
ASIC vendors often do some of the back-end design, such as

Design-for-testability (DFT) insertion (JTAG scan chain)
Test vector generation
Post-layout parasitic extraction and timing analysis
Physical and formal verification

7. Test the part

Run a complete set of test vectors using an IC tester (done by ASIC vendor)

Boundary scan using the JTAG port

TAP = Test Access Port
TCK = Test Clock
TMS = Test Mode Select
TDI/TDO = Test Data In/Out
BP = Bypass
IR = Instruction Register
ATPG = Automatic Test Pattern Generation (software)

IEEE Std 1149.1
Only connects to I/O registers

Boundary scan is intended mainly to test IC interconnects on PC board

Test vectors may achieve poor coverage in a complex part.
Serial data stream too slow for a complex part.

Scan chains

Like boundary scan, but accesses internal registers
Each register to be tested includes a multiplexer to select normal input or scan chain.
May have multiple chains, each with two inputs and an output, to speed the testing process

BIST (built-in self test)

Special circuitry on the chip runs canned test routines.
Much faster than scan chains.
Often used to test on-chip memory.

Test for proper functionality in the circuit
Most problems turn out to be definitional. The synthesis tools are nearly perfect these days.