CES 520 - WEEK 13 November 14, 2006 - High-level system design issues

Example system: The Eagle amateur radio satellite

• An amateur radio communications satellite
• Re-transmits signals from uplink frequency bands to downlink frequency bands:

UPLINK
U	UHF	435 MHz	SDX, 100 kHz bandwidth
L	L band	1.2 GHz	SDX, 100 kHz bandwidth
S2	S band	3.4 GHz	ACP, 5 MHz bandwidth

DOWNLINK
V	VHF	145 MHz	SDX, 100 kHz bandwidth
S1	S band	2.4 GHz	SDX, 100 kHz bandwidth
C	C band	5.8 GHz	ACP, 10 MHz bandwidth

• SDX = Software-defined transponder
• 100 kHz-wide bandwidth is digitized with an ADC.
• Multiple narrow-band signals on different frequencies can be either analog or digital modulation.
• Signals are demodulated and re-modulated/re-retransmitted on another band.
• A breadboarded prototype has demonstrated basic functionality.
• ACP = Advanced communications processor
• 5 MHz-wide bandwidth is digitized with an ADC.
• Multiple digital signals on different frequencies
• Signals are combined into one wideband data stream and retransmitted on another band.
• Spacecraft shape was changed to hexagonal.
• More solar cells to obtain more power.
• More space for antennas.
• Flatter shape gives more stable spin.
• The Molniya orbit is highly-elliptical orbit inclined 63.4 degrees from the equator.
• The "magic angle" gives a stable orbit.
• Eagle will be launched into a geosynchronous transfer orbit (GTO).
• Roughly equatorial orbit.
• A small rocket motor is required to raise perigee (closest approach to earth) above the atmosphere.
• Spacecraft is spin-stabilized.
• Antennas mount on top surface of spacecraft
• Antennas point to earth at apogee (point farthest from earth).
• S2 and C-band antennas will be derotated to always point to earth as the satellite rotates.
• Phased array can be rotated electronically - no moving parts.
• IHU = Internal Housekeeping Unit, the main on-board computer
• All subsystems are connected via a CAN bus.
• A standard interface card was developed to simplify the CAN bus interface.
• A series of modules of three standard sizes was developed to house the subsystems.
• Eagle includes sun and earth sensors to determine the spacecraft orientation in space
• Needed to keep the spin axis pointed to the earth at apogee.
• Needed to orient the spacecraft for rocket motor firings after launch.
• Sun sensors come in two types.
• Dual-slit sensors depend on satellite rotation for their function.
• The time difference of the signals from the two sensors indicates the elevation.
• The absolute time of the pulses indicates the azimuth.
• Staring-mode sensors work when the sun is stationary.
• A position-sensitive light detector (PSD) senses the position of the spot of light.
• PSD is covered with a transparent resistive coating. Most current flows to the closest edge contacts.
• A divider circuit outputs the normalized X and Y position.
• Earth sensors only work when the satellite is relatively close to the earth.
• Infrared sensor senses horizon crossing by measuring temperature difference of earth and space.
• A sensor angle of 60 degrees sees the earth over half the orbit.
• Eagle I will fly with commercial Horizon-Crossing Indicators (HCI).
• Also some homebrew sensors made from burglar-alarm infrared sensors.
• The output signal is very high-impedance (100 Gohms). Buffer amp is mounted in sensor housing.
• Signal is AC-coupled to sense the horizon transitions.
• Homebrew sensors were tested with a vat of liquid nitrogen to simulate the cold of space.
• Sensor Electronics Unit (SEU) includes local microprocessor with ADC to read analog signals.
• Proposed to have two separate systems for the two sets of sensors in the same housing for reduncancy.

Customer requirements

• Customers often give vague, innacurate, or inconsistent requirements.
• These must be distilled into a Customer Requirements Document
• Based on negotiations between customer and provider to determine what is feasible.
• Specifications should be consistent (realizable) and complete (implementation is uniquely defined).
• Errors in system requirements are the most expensive of all errors.
• Example: response time vs speed. "Real-time" does not necessarily mean "fast".
• Typical software development cycle is 40% requirements capture, 20% coding, 40% testing.
• Product documention should include:
• Product description: Describe what the product is.
• Functional requirements Document: What the product must do
• Engineering documentation:
• One set for each board or subsystem
• Schematic diagrams
• Circuit descriptions
• Design intent]/ theory of operation
• Often combined with the circuit description
• Block diagrams.
• PC board part location diagram
• Mechanical drawings
• Programmer's Reference for the CPU
• Software documentation:
• One for each processor or major functional block
• High-level description of code function
• Source code, header files, libraries, etc.
• Makefiles and other scripts used in building, linking, etc.
• Test requirements and specifications: What must be tested and to what specifications

Hardware vs software tradeoff

• Software is mostly a one-time cost, while hardware has a higher per-unit cost.
• Software is emphasized for high-volume applications - NRE can be amortized over many units.
• In low-volume applications, adding hardware to reduce the software task makes sense.
• "Codesign" is a buzzword for designing both HW and SW in the same process
• Some CAD (computer-aided design) software allows postponing the HW/SW decision until late in the design cycle.

Software language choice

• Assembly:
• Translates each line of source code directly into one machine instruction.
• There's a different assembly language for every processor architecture.
• Fastest and most compact.
• The best choice for very small systems.
• Easier to determine response time.
• Often used in (small) real-time systems.
• Harder to program - requires detailed knowledge of CPU architecture
• Maintenance is an issue (fewer people know assembly language)
• C is the most common choice
• A relatively low-level "high-level" language
• Closer to the hardware
• No strict type checking
• Pointers give great flexibility, but are dangerous in the wrong hands.
• Compiled code is quite efficient.
• A good optimizing compiler beats all but the best assembly-language programmers.
• Compiler may optimize speed or (less often) memory usage.
• Some optimizations can be dangerous in real-time embedded systems.
• Example: Multiple identical writes to the same address may be "optimized" out.
• C++
• Originally called "C with classes"
• Adds classes w/inheritance, many library functions, exceptions, //comments, etc.
• Larger compiler than C - has been ported to fewer architectures.
• Larger footprint than C. Requires lots of memory.
• More complicated language - fewer programmers available.
• Tends to be used in large, multi-programmer projects.
• Java
• Object-oriented
• Compiled to bytecode which is compiled at run time.
• Good for cross-platform applications
• Like C++ but not as close to the hardware (higher level of abstraction)
• Much larger runtime footprint than C.
• Unpredictable runtimes and memory usage can be a problem.
• There is a real-time Java specification that addresses some of these issues.
• C# (C sharp) is Microsoft's alternative to Java, now an ISO standard.
• Object-oriented
• Compiled to Common Interface Language (part of Microsoft .NET framework) compiled at runtime.
• C# is popular for Windows desktop software, while Java dominates mobile and web-based applications.
• Forth
• Stack-based. Interactive. Easily-extensible. Non-typed.
• Sometimes used to test/debug hardware and bring up systems
• Mainly for enthusiasts

Hardware choices

• Single vs multi-processor
• The choice may depend on the software architecture - highly-modular code is easier to partition.
• Can complicate or simplify the software.
• Parallel processors running identical code can process data streams in parallel to improve the speed.
• SIMD - Single Instruction, Multiple Data. All processors execute the same instructions.
• MIMD - Multiple Instruction, Multiple Data. Each processor executes different instructions.
• Multiple processors may or may not share memory.
• Distributed processing/networking
• Can add redundancy to allow graceful degradation from faults.
• Placing processing close to the data source/sink can reduce bandwidth requirements for comm. links.
• Processor type
• CISC: Complex Instruction Set Computer.
• A single instruction may take many clock cycles and perform complicated operations.
• Fewer instructions per operation gives reduced code size and fewer program memory accesses.
• May be easier to program in assembly.
• Examples: Intel x86, Motorola 68k.
• RISC: Reduced Instruction Set Computer.
• (Nearly) all instructions execute in single clock cycle. Most operations are simple.
• Usually has a pipelined architecture to achieve single-clock instructions.
• Harvard architecture means that program and data memory are kept separate.
• Allows simuntaneous data and instruction fetch.
• Data and program memory may be different types and different sizes.
• Large set of registers to reduce the number of data memory accesses.
• Examples: MIPS, ARM, Power PC, many small microcontrollers intended specifically for embedded systems.
• DSP: Digital Signal Processor.
• A microprocessor optimized for signal processing.
• Hardware multiplier/accumulator for digital filtering
• Modulo addressing for circular buffers, bit-reversed addressing for FFT.
• Zero-overhead looping - "Do" loops in hardware.
• Usually RISC with a Harvard architecture.
• May have SIMD (Single Instruction, Multiple Data using parallel computation units)
• Uses on-chip memory for speed. Similar to cache memory in general-purpose processors.
• Often has a relatively small memory space - DSP doesn't require large databases.

Standard embedded system platforms

• Some applications may be able to use a PC, perhaps with new operating system
• PC/104 bus
• A compact-form-factor PC. The electrical interface is the same as the old ISA bus.
• No backplane, boards are stacked and bolted together for ruggedness.
• Each stack must include at least one single-board computer (SBC) motherboard.
• Boards are 3.55 x 3.775 inches.
• "PC/104 Plus" adds an additional connector for a PCI bus
• "PCI-104" only has the PCI connector.
• Maximum 4 PCI boards without a PCI bridge.
• STD Bus
• Developed in 1978. IEEE-961.
• Small size. Easy to use. Many cards available from vendors.
• 56-pin connector with 0.125-inch contact spacing. 4.5 x 6.5-inch board size.
• 8-bit data, 16-bit address.
• "STD 32" bus has 8, 16, or 32-bit data bus and other features.
• 0.0625-inch pin spacing for backward-compatibility with "STD 80" boards.
• VME bus - Associated with larger and costlier systems.
• ANSI/IEEE-1014.
• Developed in 1981, based on the Motorola 68000 microprocessor bus.
• Uses standard Eurocard PC boards plugged into a backplane at the back of a standard rack.
• Standard board heights are in units (U) of 1.75 inches.
• Most common sizes are 3U (5.25 in) and 6U (10.5 in), which can be mixed in the same rack.
• 16 or 32-bit bus. VME64 allows 64-bit in the 6U card size.
• 40 Mbytes/sec
• VXI is an extension of VME for instrumentation.
• Compact PCI - VME form factor but with PC-type PCI backplane.
• Uses the same Eurocard card sizes as VME - 3U or 6U size
• Connectors use 2 mm pin spacing, rather than 0.1 inches as with VME
• 220 pins for 64 bits, 110 pins for 32 bits
• Up to 8 cards per segment. More cards require a PCI bridge.

Analog vs digital hardware

• As time passes, Moore's law favors digital more and more (Moore and Moore?)
• ASIC vs FPGA vs CPLD vs PAL vs discrete logic
• ASIC: Highest speed, highest density, low per-unit cost, high NRE
• FPGA: Reprogrammable, high density, high per-unit cost, no NRE
• CPLD: Reprogrammable, medium density, low per-unit cost, no NRE
• PLD: low density, lowest per-unit cost, no NRE

Choice of simulation/synthesis tools

• Some simulation tools (e.g. Matlab/Simulink, SPW) can synthesize HDL as well.
• Schematic entry vs HDL (Hardware Description Language)
• Unlike conventional computer languages which are sequential, HDLs are concurrent - they assume different parts run simultaneously.
• Verilog - A leaner HDL more directly geared toward simulating digital ICs.
• VHDL - More verbose HDL that can handle a wider class of simulation and modeling tasks.
• SystemC - Extension to C++ libraries to add hardware description capability
• Well-suited for system-level simulations

Assignments:

• Read Embedded Systems Design, Chapter 2 pp 19-35.
• Read An Embedded Software Primer, Chapter 11.