CES 520 - WEEK 15 Dcember 5, 2006 - Review
Microcontrollers
Software
- Interrupts, internal and external
- The shared data problem
- Scheduling
- Preemptive (cooperative) versus non-preemptive
- Timing
- Periodic
- Aperiodic
- Sporadic
- Schedulers
- Round Robin
- Round Robin with interrupts
- Function Queue
- Real-time Operating System
- Principles of good coding
- Component-based design
- All possible errors trapped and handled without human intervention.
- Carefully analyze worst-case timing
- Read the data sheets
- Understandable code
- Well-structured, hide details in functions
- Optimize only when necessary
- Comments, good variable names, etc.
- Documentation
- Data flow diagrams
- State diagrams
Real-Time Operating Systems
- Process versus thread
- RTOS architectures
- Preemptive vs non-preemptive scheduling
- Priority-based schedulers
- Fixed (static) priority
- Dynamic priority
- Priority inversion and deadly embrace
- Priority Inheritance Protocol
- Priority Ceiling Protocol
- Intermediate Ceiling Priority Protocol
- Interprocess Communication
- Reentrant functions and interrupt service routines
- Semaphores
- Message queue
- Mailbox: a message queue with unlimited queue size
- Pipe: Like a message queue but each message is a single byte
- Publisher/subscriber: Like message queue but with multiple receivers
- Blackboard: Global variables
- Client-server: Client asynchronously invokes the server
- Monitor: A process that intermediates all resource access
- Memory management
- Map virtual memory to physical memory
- Dynamic memory allocation - Most RTOS use fixed block sizes.
- Rules for using interrupts with an RTOS.
- An ISR may not call any RTOS function that might block the ISR.
- An ISR may not call any RTOS function that might cause a task switch. - (Unless the RTOS knows that it is being called by an ISR).
- POSIX
Debugging
- Best technique: Don't have bugs in the first place
- Debugging requires close collaboration between hardware and software engineers.
- Tools
- Oscilloscopes show things logic analyzers cannot
- Hardware/software aids
- Blinking LED
- Lots of test points
- Logic analyzer connector(s)
- Extra RAM for debugger
- Asserts/exceptions
- Power-On Self Tests
- "Dead computer" test: Socketed jumper puts CPU into endless loop
- Spare IO port plus software to capture events on a logic analyzer
- Circular trace buffer in RAM
- Memory dump with unused output pin to logic analyzer trigger input
- Debugging rules
- Check simple things first
- Don't stop until you find the root cause
- Only change one thing at a time
- Keep a troubleshooting log
- Divide and conquer
- Remember that debug hardware/software can affect system functionality
- Intermittent software
- Unitialized pointers or static variables
- Buffer/array/stack overflow/underflow
- C's malloc() function
- Execution time stackup of interrupts
- Shared data problems
- Intermittent hardware
- Setup/hold times
- Power supply decoupling
- EMI (PC board layout, shielding)
Interfacing to the external world
Customizable Logic Devices
- ROM memory
- PAL
- CPLD
- PALs and CPLDs are programmed with a simple JEDEC file
- FPGA
- ASIC
- FPGA/ASIC design process
- 1. Generate design requirements at a high level
- 2. Simulate the design at a high abstraction level
- Mathematical algorithms:
- Matlab, Mathcad, Maple, Mathematica
- Functional simulation:
- 3. Generate HDL - Hardware Description Language
- Generated automatically by simulation tool
- Hand-written
- VHDL versus Verilog versus SystemC
- Write test bench in HDL
- 4. Logic synthesis - generate the netlist
- Design Compiler, Synplify, etc.
- Verify equivalence to HDL
- Initial static timing analyxix
- 5. Place and route
- (ASIC design) Verify equivalence to netlist
- 6. Make the part
- 7. Test the part
Digital Signal Processing
Networks
- Types:
- Examples: Automotive, building automation, factory, habitat monitoring
- Communication techniques
- Field Area Networks
- Automotive
- Avionics/aerospace
- IEEE 61158
- Misc.
- 7-layer OSI model protocol stack
- Each layer only communicates with layers above and below
- Ethernet
- Nowdays normally uses twisted-pair in a star configuration
- Hub vs bridge vs switch
- A router is like a bridge that connects entire networks
- Specifies the lower two layers of the 7-layer model.
- Each frame includes a 48-bit MAC address
- Internet
- Internet Protocol: similar to OSI model, but with only 5 levels
- Transport layer
- TCP - establishes virtual circuit byte-pipe connection
- UDP - connectionless data transfer: More efficient but data delivery not guaranteed.
- Socket paradigm
- 32-bit IP address
- DNS = Domain Name System: Translates URLs into IP addresses
- Subnet mask: Restricts range of the local subnet
- DHCP = Dynamic Host Configuration Protocol: Automatically assigns IP address.
Documentation
- Customer requirements document
- Other product documentation
- Product description
- Functional requirements document
- Engineering hardware documentation
- Schematics
- Circuit descriptions
- Design intent/theory of operation
- PC board part location diagrams
- Mechanical drawings
- Programmer's reference for the CPU
- Software documentation
- High-level description
- Source code, header files, libraries, etc
- Makefiles and other scripts
- Defect tracking records
- Test plan
Test and Verification
- Static testing
- Formal verification
- Peer reviews
- Dynamic testing
- Performance analysis tools
- Instrumented versus sampling profilers
- Code coverage
- Regression testing
- Black-box versus white-box testing
- Stress testing
- Usability testing
- Timing analysis
- Test levels
- Unit
- Integration
- System
- Acceptance
