;
; id_dec.pds
; $Id: io_dec.pds 1.1 1999/02/23 14:26:10 frago Exp frago $
;
; PALASM Design Description
;
; I/O decode circuit for Z80180 production board.
; Decodes CE for local watchdog reset, output and input ports.
; Also contains logic for bus driver direction and internal/external reset.
;
; Schematic device: D7
;
; Address map [hex]
;   40  INPUT_EN
;   50  WD_RESET
;   60  LATCH1

;---------------------------------- Declaration Segment ------------
TITLE    IO_DEC.PDS
PATTERN  A
REVISION 1.0
AUTHOR   F Gormarker
COMPANY
DATE     990222

CHIP  IO_DEC  PAL16V8

;---------------------------------- PIN Declarations ---------------
PIN  1          MREQ                 COMBINATORIAL             ; INPUT
PIN  2          IORQ                 COMBINATORIAL             ; INPUT
PIN  3          RD                   COMBINATORIAL             ; INPUT
PIN  4          M1                   COMBINATORIAL             ; INPUT
PIN  5          WR                   COMBINATORIAL             ; INPUT
PIN  6          A19                  COMBINATORIAL             ; INPUT
PIN  7          A7                   COMBINATORIAL             ; INPUT
PIN  8          A6                   COMBINATORIAL             ; INPUT
PIN  9          A5                   COMBINATORIAL             ; INPUT
PIN  10         GND                                            ; INPUT
PIN  11         A4                   COMBINATORIAL             ; INPUT
PIN  12         RESET                COMBINATORIAL             ; OUTPUT
PIN  13         WD_RESET             COMBINATORIAL             ; OUTPUT
PIN  14         LATCH1               COMBINATORIAL             ; OUTPUT
PIN  15         RESET_FROM_WD        COMBINATORIAL             ; OUTPUT
PIN  16         XRESET               COMBINATORIAL             ; INPUT
PIN  17         INPUT_EN             COMBINATORIAL             ; OUTPUT
PIN  19         BDIR_IN              COMBINATORIAL             ; OUTPUT
PIN  20         VCC                                            ; INPUT


;----------------------------------- Boolean Equation Segment ------
EQUATIONS

/RESET = /XRESET + /RESET_FROM_WD

/BDIR_IN = /MREQ * /RD * A19 + /IORQ * /RD * A7 + /M1 * /IORQ

/INPUT_EN = /IORQ * /A7 * A6 * /A5 * /A4

/WD_RESET = /IORQ * /WR * /A7 * A6 * /A5 * A4

/LATCH1 = /IORQ * /WR * /A7 * A6 * A5 * /A4


;----------------------------------- Simulation Segment ------------
SIMULATION
TRACE_ON RESET INPUT_EN WD_RESET LATCH1

SETF  IORQ MREQ RD WR /A7 /A6 /A5 /A4 /A19
CHECK INPUT_EN WD_RESET LATCH1 RESET

TRACE_OFF
;-------------------------------------------------------------------