[an error occurred while processing this directive] Jack Ou -

 

Course:Cadence

Instructor:  Jack Ou, Ph.D.
Office Location: Salazar Hall 2010B
Telephone: (707) 664 3462
Email:jack.ou AT sonoma DOT edu


Analog/Transistor Level Design

Topic
Details
Obtain DC annotation
Determine the small signal parameter of a BJT
set the initial condition of a capacitor
Obtain the oscillator frequency
An oscillator modulated by a square wave
DC analysis of an inverter
DC sweep of an inverter

 

Verilog Simulation

Topic
Comments
Detect a zero after a string of ones.
Logic synthesis using Encounter