CES 522

Course:VLSI Design (CES 522)
Section: 001
Fall, 2011

Instructor: Jack Ou, Ph.D.
Office Location: Salazar Hall 2010B
Email:jack.ou AT sonoma DOT edu
Office Hours: By appointment during MW11:30-12 and TTH 10:35-11

Course Description:

IC technology review; hardware description languages and describing hardware using one of the languages, modern VLSI design flow; circuit partitioning; clustering. Floorplanning; placement; global routing; area efficient design, area-time trade-offs.

Textbook:

1. (Requried) David A. Hodges, Horace G. Jackson, Resve A. Saleh, “Analysis and Design of Digital Integrated Circuits,” McGraw-Hill, 2004. ISBN: 0-07-228365-3.

2. (Optional) Neil Weste and David Harris, “CMOS VLSI Design: A Circuits and Systems Perspective.” ISBN 10: 0-321-54774-8.

3. J. Ou, "Mentor Graphics Custom IC Design Tutorial", 2011.

4. J. Ou, "Project Manual for CES522", 2011.

Date	Topic	Verilog	Layout	Homework	Solution
8/29	VLSI Design Hierarchy	Chapter 1	N/A	HW1	N/A
9/12	Short Channel CMOS Derivations	Chapter2	N/A	HW2	N/A
9/19	Capacitance	Numbers,Test Methodology, Propattion Delay	N/A	N/A
9/26	CMOS Inverter	Vector test, assign, enable	N/A	HW3	N/A
10/3	Static CMOS Gates	blocking/nonblocking	CMOS Inverter	HW4	HW4
10/10	Latches/Flip-Flops	N/A	N/A	N/A	N/A
10/17	Delay, Supplement	Selected Combinatorial Circuit	N/A	HW5	HW5
10/24	Logical Effort (1) Supplemental HO	N/A	N/A	CMOS Inverter Project
10/31 11/7	Logical Effort (2)	Verilog/Transistor Simulation	Random Notes on Layout	HW6	HW6
11/14	Section 7.2-7.3	Transmission Gate		Mixed Signal Simulation Project Due	N/A
11/28	Section 7.4-7.5, Misc Notes	Transmission Gate, Dynamic Logic		HW7
12/5	SRAM, HO	8.1-8.3.3		N/A
12/12	Final (4:30p.m.-6:20 p.m.) Review Notes