[an error occurred while processing this directive] CES 522

Course:VLSI Design (CES 522)
Section: 001
Fall, 2011

Syllabus

Instructor:  Jack Ou, Ph.D.
Office Location: Salazar Hall 2010B
Email:jack.ou AT sonoma DOT edu
Office Hours: By appointment during MW11:30-12 and TTH 10:35-11

 

Course Description:

IC technology review; hardware description languages and describing hardware using one of the languages, modern VLSI design flow; circuit partitioning; clustering. Floorplanning; placement; global routing; area efficient design, area-time trade-offs.

 

Textbook:

1. (Requried) David A. Hodges, Horace G. Jackson, Resve A. Saleh, “Analysis and Design of Digital Integrated Circuits,” McGraw-Hill, 2004.  ISBN: 0-07-228365-3.

2. (Optional) Neil Weste and David Harris, “CMOS VLSI Design: A Circuits and Systems Perspective.”  ISBN 10: 0-321-54774-8.

3. J. Ou, "Mentor Graphics Custom IC Design Tutorial", 2011.

4. J. Ou, "Project Manual for CES522", 2011.

Date
Topic
Verilog
Layout
Homework
Solution
8/29
Chapter 1
N/A
N/A
9/12
Chapter2
N/A
N/A
9/19
N/A
N/A
9/26
N/A
N/A
10/3
10/10
N/A
N/A
N/A
N/A
10/17
N/A
10/24
N/A
N/A
CMOS Inverter Project
10/31 11/7
Logical Effort (2)
Verilog/Transistor Simulation
11/14
Transmission Gate
N/A
11/28
Transmission Gate, Dynamic Logic
12/5
8.1-8.3.3
N/A
12/12 Final (4:30p.m.-6:20 p.m.) Review Notes