[an error occurred while processing this directive] Jack Ou -

Course:Digital Circuits and Logic Design (ES 210)
Section: 001
Spring, 2013

 

Instructor:  Jack Ou, Ph.D.
Office Location: Salazar Hall 2010B
Telephone: (707) 664 3462
Email:jack.ou AT sonoma DOT edu
Office Hours: By appointment during MW10:15-10:45 and TH 12:30-1
Class Days/Time: MW 1:00-2:15. Lab: T 1:00-3:45 (SAL 2003)
Classroom: Salazar Hall 2009A
Prerequisites: ES 112
Co-requisites: ES 230

Course Description

Logic gates, combinatorial logic and analysis and design of combinatorial circuits, electronic circuits for various logic gates. Flip-flops, registers, and counters, sequential circuits and state machines. Various logic families and comparison of their electrical characteristics such as fan-out, rise and fall times, delay, etc. Concepts of machine, assembly and high level languages and relationship between them, basic principles of computer design. Laboratory work will include designing, building and testing of digital circuits, logic and sequential circuits.

Required Materials:
1.  M. Morris Mano and Michael D. Ciletti, “Digital Design”, 4th Edition, Prentice Hall, ISBN 0-13-198924-3
2.  Basys 2 Spartan-3E FPGA Board.  (49.00)

3. Digital Design Using Digilent FPGA Boards (44.95, Verilog edition)

4. ES210 Lab manual

5. Hardware components , list of 7400 TTL gates.

 

Syllabus, project ideas

Date
Topic
Description
1/14
1/15
No lab!
1/16
555 timer IC, ring oscillator, astable multivibrator, monostable circuit
1/21
MLK Day
1/22
555 Timer IC
1/23
ADC, DAC
1/28
Basys2
1/29
first basys2 lab
1/30
verilog syntax, gate delay, test bench,implement a full adder on FPGA.
2/4
Karnaugh map, hex to seven-segment display,
2/5
full adder,demo
Verilog/74XX Implementation of a full adder
2/6
2/11
carry_lookahead demo, ripple adder, binary adder with fast carry, implement a subtractor using an adder
2/12
4-bit binary adder with fast carry
verilog modeling and 7483 four bit adder with look-ahead carry
2/13
2/18
N/A
2/19
Implment binary add/subtractor
2/20
2/25
PCB layout
2/26
Intro to Eagle
2/27
2-bit binary multiplier, adder-based multiplier circuits, magnitude comparator
3/4
test bench generation, decoder
3/5
PCB fabrication
3/6
3/11
sr latch, d-latch
3/26
d-latch experiment
3/27
D flip-flop, JK flip-flop, T flip-flop, Phase-frequency detector
4/2
d-latch with random number generator
mixed signal scope, random number generator
4/3
state diagram, synthesis using d flip-flop
4/8
Verilog modeling of FSM
4/9
Design a Mealy Type FSM (lab)
4/10
serial adder, shift register, universal shift register
4/15
Final Project
4/16
shift registers lab
4/17
4/18
Overview of Digital IC Design from 4:30 to 5:30 pm.
4/22
Proposal for Final Project Due
4/23
counters lab
Meet to Discuss Project. Begin to work on the final project!
4/24
4/29
4/30
SRAM lab
5/1
Test #2
5/8
Final Project Due
2-3:50 pm