Jack Ou, Ph.D.
Assistant Professor, Engineering Science, Sonoma State University
Ph,D., M.S., and B.S. Rutgers University (Piscataway Campus)
Research Interest: Low power CMOS analog/RF integrated circuits
Low Power Oscillator Circuit Design for Wearable Applications.
Selected Publications Since Joining SSU:
Ou, J. and Ferreira, P., “Transconductance/Drain Current Based Sensitivity Analysis for Analog CMOS Integrated Circuits”, International NEWCAS Conference, Paris, France, June 2013
Ou, J., and Farahmand, F., “Transconductance/Drain Current Based Distortion Analysis for Analog CMOS Integrated Circuits,” International NEWCAS Conference, Montreal, Canada, June 2012.
Ou, J., “Transconductance/Drain Current Based Noise Analysis for CMOS Analog Circuit,” IEEE International Midwest Symposium on Circuits and System, Seoul, Korea, August, 2011.
Transconductance/Drain Current Based Sensitivity/Distortion/Noise Design Methodology.
VerilogAMS Verification of a Low Density Parity Code (LDPC) Forward Error Correction Ciruit.
Voltage Controlled Oscillator in 180 nm/65 nm CMOS.
A WCDMA Downconverter circuit in 90nm/65 nm CMOS.
A High Frequency Distributed Current Commutating Mixer.
Inductor/Transformer/Transmission Line Modeling.
Inductance Calculation of Complex Internnect
Selected Presentations with Undergraduate Students:
Ou, J., Saephan, C., Maldonado, A., Kikuchi, J., Farahmand, F., and Caggiano, M., “A Low-Cost PCB Fabrication Process,” Electrical Components and Technology Conference, Orlando, Fl, May 2014.
Saephan, C. and Ou, J., “Design and Fabrication of an RF Band-Pass Filter,” Oral Presentation at ES-Agilent Summer Research Academy, July 2013.
Tran, D and Ou, J., “A Digital Notch Filter for an ECG Circuit” CSUPERB, Stanta Clara, CA, January, 2014.