Decoders and Demultiplexers

Objective

To design and study decoders and demultiplexers

Decoder:

  1. A 2-4 decoder is a network with two inputs (X0 and X1) and 4 outputs (Y0, Y1, Y2 and Y3). When the inputs are both 0, Y0 = 1 and the other outputs are 0. When the inputs are 0 and 1 respectively, only Y1 is 1. For 10 and 11 inputs only Y2 and Y3 are 1 respectively. Write the truth table. Using NAND gates design a 2-4 decoder. Demonstrate the circuit to your instructor.
  2. Study the specification of a 74155 chip, a dual 2-4 decoder. From the truth table in the specs, derive the logical expression of the outputs.
  3. Draw the wiring diagram to make the 74155 into a 3-8 decoder. Wire up the circuit and verify the operation.

Demultiplexer:

A demultiplexer is a combinational circuit with:

n control (or select) lines: C1,..., Cn
2n output lines: f0, f1,..., f(2n)-1
One input line: I

Demultiplexer
Figure 1 - Demultiplexer

A demultiplexer receives binary information on a single line (I) and transmits this information on one of 2n possible output lines. The selection of a particular output line is controlled by minterms of control lines.

  1. Design and implement a 1-4 demultiplexer using NOT and AND gates. Demonstrate the circuit to your instructor.
  2. Connect the input I to hi. Write the truth table of this circuit and identify its operations.
  3. A 74155 can also be used as a demultiplexer, i.e., it can function like a rotary switch to demultiplex a single input to four different output lines. The select lines control the rotary switch position digitally. Wire up the 74155 as a 1-4 line demux. Connect the outputs to the LED's. Connect the select lines to the switches and change the settings from 00 to 11. Observe what happens.

1 to 4 Line Demultiplexer
Figure 2 – 1 to 4 Line Demux

Design Problems:

  1. Using a 3-8 decoder and three 2-input OR gates, design a combinational multiple output system to implement the following functions:

    f1(A,B,C) = BC + A'B'C
    f2(A,B,C) = BC + ABC'

  2. In computer systems the memory address is decoded to select a particular word. Assuming that a computer has 64 words and 6 bits to address the memory, using 74155s as a 3-8 decoder, design a 6 to 64 decoder.
  3. Using 74155 as a 3-8 decoder, design a 5 to 32 decoder.