Sequential Logic Analysis
To analyze the operation of sequential circuits, deriving their timing and state diagrams
- Analyze the following sequential circuit by deriving the state table and the state diagram.
- Determine the timing diagram for J1, J2, K2, Q1, Q2 and Z
(Assuming initially that Q1 = Q2 = 0).
- Implement the circuit using either 7473 or 7476. Obtain the timing diagram for the inputs in 1-b. Compare results.
- Apply the input sequence derived in 1-c. Read the output and next states and compare the results. Demonstrate your circuit to the instructor.
- Repeat all of part 1 for the following circuit: