## DESIGN AND CHARACTERISTICS OF THE COMMON EMITTER AMPLIFIER

### Objective:

The objective of this experiment is to design a common emitter amplifier using a bipolar junction transistor and to study the characteristics of the designed amplifier. Part of the design requirement is that the amplifier will exhibit maximum symetrica1 swing in the collector current for a stable Q-point. Another objective of this experiment is to study the impact of various bypass and coupling capacitors on the overall performance of the common emitter amplifier. This experiment will use transistor type 2N3904.

### Introduction:

The basic BJT amplifier circuit like the one shown in Figure 1 can be designed to exhibit various desirable characteristics. An important decision involved in designing this amplifier is the choice of the operating point (Q-point). This operating point refers to the amount of DC bias current that flows through the transistor. It also refers to the resulting DC voltages across its junctions. The Q-point of such a circuit can be placed anywhere on the DC load line, depending on the choice of the DC equivalent circuit component values. The location of the Q-point determines the distortion characteristics of the AC signal. By properly locating the Q-point, the symetrica1 peak-to-peak swing of the AC collector current can be maximized. In general, the DC load line must bisect the AC load line in order to allow the maximum amount of symmetrical variations in IC. It is also possible to design a circuit to obtain a particular value of ICQ. In this case, the location of the Q-point determines the maximum amount of symmetrical swing of the collector current as well as the maximum amount of undistorted voltage swing in the load resistor.

### Pre-Lab work:

Design the circuit shown in Figure 1 by calculating the values of R1, R2, RC and RE. 2N3904 NPN transistor is to be used. In this design the bias voltage between emitter and collector should be 5V DC. The quiescent collector current is 4mA. The design should provide maximum possible voltage swing at the amplifier output.

Figure 1 - Circuit Diagram for the Design Problem

### Lab work:

1. Connect the amplifier circuit you designed. Add capacitors C1, C2, and C3 as shown in Figure 2. Each of these capacitors is 10 µF. Make sure the positive polarity of these capacitors are connected to the higher positive voltage in the circuit. Take RL to be 1 kΩ. Measure the DC bias voltages on the base, emitter and the collector. Compare the measured voltages with the design intent and calculation. Tabulate the measured versus the calculated bias voltages.

2. Figure 2 - Amplifier Circuit Under Test
3. Measure the frequency response of the amplifier starting from 100 Hz. change the test frequency to cover the upper cut-off frequency of the amplifier. Throughout the measurement of the frequency response, apply low input signal levels (in the order of few milli-Volts) to ensure that the output signal is not distorted. Monitor both input and output waveforms on the oscilloscope.
1. Plot the obtained frequency response. On the measured plot clearly indicate the lower and upper cut-off frequencies of the amplifier.
2. What is the mid-band gain of the amplifier?
3. Calculate the amplifier bandwidth.
4. Change C1 to 0.1 µF and repeat the measurement performed in (2) above. Answer the following questions;
1. What impact this capacitor has on the cut-off frequencies of the amplifier? What impact it has on the amplification bandwidth?
2. What impact it has on the mid-band gain of the amplifier?
3. Why this capacitor has such an impact on the performance of the amplifier?
5. Change C1 back to 10 µF but disconnect capacitor C2. Measure the frequency response of the amplifier.
1. Plot the obtained frequency response. On the measured plot clearly indicate the lower and upper cut-off frequencies of the amplifier.
2. What is the mid-band gain of the amplifier? How does it compare with that obtained in (2.b)?
3. Why this capacitor has such an impact of the mid-band gain of the amplifier?