Objective:

To study the SR, D, JK and T Flip-flops

  1. Introduction:

    The logic devices studied to this point have all required a continuous input level to operate. Once the input level was removed, the device would not remember its previous input condition. In addition to gates, a computer requires devices that will retain their conditions after an input has been removed. One device that has memory is called a flip-flop. It is an electronic logic element that remembers the last instruction it receives. In many ways it is similar to a light switch. If a flip-flop receives an instruction to go to the 1-condition, it does so and stays there until instructed to go to the 0-condition. If it is in the 1-condition and receives an instruction to go to the 0-condition, it does so and stays there until instructed to return to the 1-condition. All flip-flops have a Q and a Q' outputs. If the Q-output is hi, it indicates that the flip-flop is in the 1-condition. If the Q output is lo, the flip-flop is in the 0-condition. The Q'-output always presents the opposite or complement of the information at the Q-output. There are, therefore, only two possible output conditions, either the Q-output is hi and Q'-output is lo or the Q-output is lo and the Q'-output is hi. In this experiment, different types of flip-flops will be constructed using only NAND gates. This permits closer study than would be possible using the complete flip-flop chips as such.

  2. Set-Reset (SR) Flip-Flop:

    The Set-Reset (SR) is the simplest to construct and easiest to understand. It has two inputs, a SET input and a RESET input, and two outputs, Q and Q'. If a hi pulse is received on the SET input, the flip-flop goes to the 1-condition and remains there after the pulse has been removed. If a hi pulse is received on the RESET input, the flip-flop goes to the 0 condition and remains there.

    SR Flip-Flop
    Figure 1 - SR Flip-Flop

    1. Construct the SR flip-flop in Figure 1 and fill out the last two columns of the table below. Demonstrate your circuit to your instructor.

      Table 1 - SR Flip-Flop Truth Table
      S R Q(present) Q(next) Q'(next)
      0 0 0    
      0 1 0    
      1 0 0    
      1 1 0    
      0 0 1    
      0 1 1    
      1 0 1    
      1 1 1    

      Give special attention when both inputs are 1. Are the outputs Q and Q' complementary? Depress both pulsers and try to release them at the same time. Is there a definite value for the final output? What does determine the value of the final output?

    2. Design an SR flip-flop using NOR gates and explain its operations.

  3. Clocked SR Flip-Flop:

    Most often when a flip-flop is used it is best to enable, or condition, its inputs with levels first and then allow it to make the required transition after it receives a pulse from the system clock. Figure 3 shows the same flip-flop with gated inputs. Study the operation of input NAND gates. When will a 1-pulse propagate to the input of the flip-flop? Construct the circuit and verify its operations. When does the flip-flop transition take place, on the leading or the trailing edge of a 1-pulse?

    Demonstration of leading and trailing edges of a pulse
    Figure 2 - Demonstration of leading and trailing edges of a pulse

    Clocked NAND gate RS Flip-Flop
    Figure 3 - Clocked NAND gate SR Flip-Flop

    Verify the operation of the flip-flop shown in Figure 3 by completing the following timing diagram (Q). Assume Q = 0 initially.

    Timing Diagram for Clocked NAND gate RS Flip-Flop
    Waveform 1 - Timing Diagram for Clocked NAND gate SR Flip-Flop

  4. Complementary (D) Flip-Flop:

    One way of insuring that there can be no indeterminate state in the operation of a flip-flop is to provide only one input, the D (complementary) input. Construct the circuit in Figure 4 and verify its operation. Does it trigger at the leading or trailing edge of the pulse? Show the truth table.

    D Flip-Flop
    Figure 4 - D Flip-Flop

  5. Clocked JK Flip-Flop:

    One of the most useful flip-flops is the JK flip-flop. A JK flip-flop has three inputs; J, K and CK. A clock at CK will cause the flip-flop to set to 1-state if the input to J and K are 1 and 0 respectively. A pulse at CK will cause the flip-flop to reset to 0 state if the input to J and K are 0 and 1 respectively. A clock at CK will cause the flip-flop to complement its state if the input to J and K are both 1. There is no indeterminate condition in the operation of a JK flip-flop.

  6. Master-Slave JK Flip-Flop:

    A master-slave JK flip-flop is actually made up of two flip-flops, a master flip-flop and a slave flip-flop. The information which is present at the J and K inputs is transmitted to the master flip-flop on the leading edge of a hi pulse and held there until the trailing edges of the CK clock occurs when it is allowed to pass through to the slave flip-flop. If the J input is enabled and the K input is disabled prior to a CK pulse, the flip-flop will go to the 1-state. If the K input is enabled and the J input is disabled prior to the CK pulse, the flip-flop will go to the 0-state. If both the J and K inputs are enabled, the flip-flop will complement on the trailing edge of the pulse and go to the opposite of whatever state it was previously. If neither the J nor the K is enabled before the pulse, the flip-flop will remain in whatever condition it was in.

    Master-Slave JK Flip-Flop
    Figure 5 - Master-Slave JK Flip-Flop

    Study the operation of the Master-Slave JK flip-flop. Show the truth table. Assuming that both master and slave flip-flops are reset to the 0 state, find the output waveforms at the terminals of both flip-flops, if the following waveforms are input to the J, K, and CK inputs. Ignore the delays in the gates and flip-flops.

    Input Waveform for Master-Slave JK Flip-Flop
    Waveform 2 - Input Waveform for Master-Slave JK Flip-Flop

    Construct the circuit in Figure 5 and verify its operation. Demonstrate it to your instructor.

    1. Convert a JK flip-flop to a D flip-flop.

      To make this conversion, we need to design a combinatorial network whose inputs are D and Q and whose outputs are J and K as indicated in Figure 6.

      JK to D Flip-Flop design
      Figure 6 - JK to D Flip-Flop design

      Therefore, we are looking for the following Boolean expressions:

      J = f1(D, Q)
      K = f2(D, Q)

      Note that the Q and Q(K+1) of JK and D flip-flops are the same. The procedure is:

      1. Write the truth table of the desired D flip-flop;

      2. Taking into account that the QK and QK+l of JK and D flip-flops are the same and using the values of the present and next state, one can obtain the required input conditions for J and K;

      3. Use K-maps to find the Boolean expressions for J and K.

        Connect up one of your JK flip-flops as a D flip-flop and verify its operation.

    2. Toggle (T) flip-flop:

      Connect up a JK flip-flop as a T flip-flop. Verify the operation and show its truth table.