555 TIMER

OBJECTIVE:

In this experiment, a 555 is used to build a simple signal source. When connected to a 5-volt supply, the circuit is directly compatible with TTL. It may also be used with any supply from 4 to 15 volts and can source or sink several hundred mA at the output if needed.

INTRODUCTION:

In 555 circuits, the timing capacitor always has one end connected to ground, and a positive-only current is applied. This allows using large electrolytics for long timing periods. The input has a very high impedance, making it possible to use high-value resistors and small capacitors for a given time constant. One can easily get a 1000:1 frequency range out of a single capacitor simply by changing the series resistor. A block diagram of the 555 is shown in Figure 1.

Block diagram of a 555 Timer
Figure 1 - Block diagram of a 555 Timer

The astable or signal source connection appears in Figure 2. Assume that the output is high (1), the charge on the capacitor low, and the "discharge" transistor is not conducting. The capacitor now begins charging through R1 and R2 in series toward the +5-volt supply. When the voltage across the capacitor gets to 2/3 of the supply, the "threshold" comparator senses this and flips the internal circuitry to the other state. The output now goes low (0), and the discharge transistor turns on. The capacitor now discharges through resistor R2. Discharge continues until the capacitor voltage drops to 1/3 of the supply voltage. At this instant, the "trigger" comparator senses the capacitor voltage and flips the circuit back to its initial state. The cycle continuously repeats, and the output is a rectangular waveform. The output is high while the capacitor is charging and low while the capacitor is discharging.

Astable or signal source connection
Figure 2 - Astable or signal source connection

The following equations show how to choose the timing resistors and calculate different parameters of the circuit.

Charge Time (Output High): 0.693 (R1 + R2) C
Discharge Time (Output Low): 0.693 (R2) C
Period: 0.693 (R1 + 2R2) C
Frequency: 1.44/((R1 + 2R2) C)
Limits: Max R1 + R2: 3.3 MΩ
Min R1 or R2: 1 kΩ
Min Recommended Capacitance: 500 pF
Max Capacitance: Limited by Leakage
Duty Cycle: Time High/Period = (R1 + R2)/(R1 + 2R2)

With a TTL 5-volt supply, these can range from 1K (minimum value-R1 or R2) through 3.3MΩ (maximum value-Rl and R2 in series). This gives a potential adjustment range of 3300:1. Best results are obtained with capacitors of 1000 pF or larger, but smaller values can be used with lower values of R1 and R2. The maximum operating frequency is around 1MHz, but best operation is obtained below 300 kHz. The minimum operating frequency is limited only by the size and leakage of the capacitor you use. For instance, a 10uF capacitor and a 3.3MΩ resistor will give a time interval of 23.1 seconds if the leakage of the capacitor is low enough. By making R2 large with respect to R1, one can get an essentially symmetrical square-wave output. For instance, if R1 is 1k and R2 is 1MΩ, the difference in charging and discharging resistance is only 0.1%, and good symmetry results. Any symmetry from 50 through 99.9% can be obtained by a selection of the ratio of R1 and R2. Figure 3 shows how we can achieve a perfectly symmetrical output by adding a clocked flip-flop binary divider to the output. The output of the clocked flip-flop will be one-half the frequency of the 555 and the symmetry will be 50-50, independent of the ratio of R1 to R2. This technique works with any signal source and may be used where a constant or exact symmetry is needed. The additional gates seen in Figure 5 select the signal at the output.

A clocked J-K Flip-Flop divides the output frequency of 555 in half with 50% duty cycle.
Figure 3 - A clocked J-K Flip-Flop divides the output frequency of 555 in half with 50% duty cycle.

PRE-LAB WORK

  1. Using the values of the resistors and the capacitor in Figure 4 and applying them in the design equations find the frequency and the duty cycle and write those in a table.
  2. Predict the frequency and the duty cycle of the waveform at the output of 74LS76N in Figure 3.

LAB WORK

Build the circuit in Figure 4 and display the resulting waveform on an oscilloscope.

Signal source circuit
Figure 4 - Signal source circuit

  1. Find the frequency and the duty cycle of the signal.
    Add the 74LS76N to the previous circuit as in Figure 3. Again, find the frequency and the duty cycle at the output of the device.
  2. Add the remaining components as shown in Figure 5 to the circuit in Figure 3. For the switch, use a wire and connect it from VCC to either of the AND gates.

Complete circuit with the data selector
Figure 5 - Complete circuit with the data selector